Another small tip your 98304 is wrong. The pll setup for optimus is
pll0_960_pll1_245_pll2_1200
the one you ganked that from has pll setup of
pll0_196_pll1_960_pll2_1200
Code:
[B]struct[/B] clkctl_acpu_speed {
[B][COLOR=#445588]unsigned[/COLOR][/B] [B][COLOR=#445588]int[/COLOR][/B] use_for_scaling;
[B][COLOR=#445588]unsigned[/COLOR][/B] [B][COLOR=#445588]int[/COLOR][/B] a11clk_khz;
[B][COLOR=#445588]int[/COLOR][/B] pll;
[B][COLOR=#445588]unsigned[/COLOR][/B] [B][COLOR=#445588]int[/COLOR][/B] a11clk_src_sel;
[B][COLOR=#445588]unsigned[/COLOR][/B] [B][COLOR=#445588]int[/COLOR][/B] a11clk_src_div;
[B][COLOR=#445588]unsigned[/COLOR][/B] [B][COLOR=#445588]int[/COLOR][/B] ahbclk_khz;
[B][COLOR=#445588]unsigned[/COLOR][/B] [B][COLOR=#445588]int[/COLOR][/B] ahbclk_div;
[B][COLOR=#445588]int[/COLOR][/B] vdd;
[B][COLOR=#445588]unsigned[/COLOR][/B] [B][COLOR=#445588]int[/COLOR][/B] axiclk_khz;
your entry of
{ 1, 98304, ACPU_PLL_0, 4, 1, 98304, 0, 3, 49152 }
lets label these as
{ 1 a, 98304 b, ACPU_PLL_0 c, 4 d, 1 e, 98304 f, 0 g, 3 h, 49152 i }
a. 1 means make freq scalable ie. basically on. 0 is off
b. 98304 is the freq khz (this is only used for human eyes and in table as its not the actual freq) true cpu_freq is defined in step e
c. acpu_pll_0 is the pll you are using
d. 4 is the src sel which is a11clk_src 4 which is pll 0 whose clk is 960mhz
e. (this line determines the actual freq) 1 is the divider which is x+1 which will mean a divider of 2 against the pllclk you are using in this case pll0 which runs at 960mhz on this phone. So that would be 960/2 = 480mhz or 480000khz
f. the 93804 is the ahbclk (like the bus in pc overclocking) this freq is only for human eyes and doesn't represent the actual value. The actual calculation for it is below
g. divider is 0 so its x+1 which would be a divider of one. With your actual freq of 480000khz your entry in line above is actually 480000khz as being read by machine.
h. the 3 is the vdd level for voltage 3 is min stable voltage it seems. 3-6 are same voltage and 7 is max voltage
below is what they actually mean but they aren't labeled as such in code aurora source.
Code:
[I]Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */[/I]
enum {
VDD_0 = 0,
VDD_1 = 1,
VDD_2 = 2,
VDD_3 = 3,
VDD_4 = 3,
VDD_5 = 3,
VDD_6 = 3,
VDD_7 = 7,
VDD_END
};
i. the 49152 is the axiclk_freq which max is 200mhz on msm7x27
your entry is actually running an alternate 480mhz with the ahbbus way overclocked and the axiclk too low.
I case you were wondering this line is changing the above divider rules for the overclocking but only at freq above 600mhz.
Code:
a11_div [B]=[/B] hunt_s[B]->[/B]a11clk_src_div;
[B]if[/B](hunt_s[B]->[/B]a11clk_khz[B]>[/B][COLOR=#009999]600000[/COLOR]) {
a11_div[B]=[/B][COLOR=#009999]0[/COLOR];
writel(hunt_s[B]->[/B]a11clk_khz[B]/[/B][COLOR=#009999]19200[/COLOR], PLLn_L_VAL([COLOR=#009999]0[/COLOR]));
udelay([COLOR=#009999]50[/COLOR]);
}
for example
{ 1,
864000, ACPU_PLL_0,
4,
0,
216000,
3,
7,
122880 },
its taking 864000/19200 = 45 and writing 45 using the ACPU_PLL_TCXO clk multiplier which is 19200. This results in underclocking pll0 to 864000khz and dividing it by a11_div=0 which is x+1 so its using pll0 at 8640000/1 instead of using the normal 960000khz/ (divider in freq table) of pll0. Its actually underclocking the pll0 which normally runs at a static 960mhz.
