The term you're looking for is low-k interconnect material.
The theoretical limit for CMOS manufacturing is about 0.5 nm process technology, according to the ITRS, but you're free to correct me, the 2010 posts are -
2010 Update
Samsung achieved 22 nm memory manufacturing just within the last year, and work is afoot to get to sub-20 nm processes earlier than the ITRS roadmap suggested.
You're off by a factor of around 300.
I have no idea what you meant there.
You have no idea what you meant there.
OK.
Qualcomm is a
fabless company, if we look only at their semiconductor side.
They achieve a lot in design.
They achieve really nothing in semiconductor production - that's contracted out to firms like TSMC. I prefer to not comment on which of their fabs produce which products, but these links provide reading of interest to some, especially the details with respect to dates.
Qualcomm and TSMC Collaborating on 28nm Process Technology
TSMC's Fab 6 Production Exceeds 70,000 8-inch Wafers per Month
Evidently, you don't work in hardware or in hardware supply.
Neither are you familiar with semiconductor manufacturing. Nothing is achieved in production at the last minute.
@EarlyMon, Since it slow around here today and basically everything is already been ported or tested. I guess use your example of taking things out of context and pasting together posts to make some point?
Matter fact there was company that first used copper in a semi conductor manufacturing. IBM first used copper manufacturing process in 1997. IBM also found out the hard way how volatile copper contamination was. Simple hair strand of copper cross contaminated into a non copper processing tool. Destroying every single wafer processed through that tool and on down manufacturing line after that. "I have seen under electron microscope what happens to metal oxide contaminated by copper and the die's all look like rust" End result was IBM's entire fab was shut down and "Billions" of dollars lost. Intel was the "first" to prefect the copper manufacturing process. That bullet taken care of, let's move on shall we...
"I think the word you looking for is low "K" interconnect material"
Interconnect material? No we use a material called ILD "Inter laminated dielectric" It used to isolate one metal layer of the die to the next metal layer. ILD also act like a capacitor for the interconnects between the metal layers. FYI, there are 7 metal layers and 6 ILD layers in a single Intel CPU core.
Copper process I am talking about is accomplished like this.
1)You have a bare 300mm (12in) Silicon wafer it goes over to planner to have very thin layer of metal oxide poured and polished over it.
2)Wafers then sent over to "Thin Films" to have a very then layer of resist spun onto the entire surface of the wafer.
Maybe this is what you are talking about (K) interconnects? The resist layer has inductive/capacitive/resist properties that come into play later, but ultimately this is what we call sacrificial layer as it is removed at the end of the metal layer process in manufacturing.
3)The wafer is put back into a cassette holding 24 other wafers making 25 total wafers for each cassette goes into what is called a "Boat". The boat through automation is sent over to etch "WetEtch" where a material called SLAM "Superficial Light Absorbing Material" is applied by "dunking" the cassette holding all the wafers into a bath module inside a "WetBench". Once again all handled through automation. The Wetbench tool will reach in grab the cassette from the "boat" and transport the cassette to the desired module and preforms the process. The "Wetbench" can do this with up to 12 cassette all at the same time, impressive if you do the math, because 300 wafers being processed all at once. A company by EATON manufacture the wetbench tool. SLAM absorbs some of the light during the exposure process(Lithography) as to not distort images being applied to the surface of the wafer. Because the die scale shrunk and we had the light intensity up so high during the exposure the light would reflect back and killed the die during the etching process. Intel invented a material called "SLAM" to remedy this. Each 12in wafer is equal to 1260 dies. Means a crap load of intel processors on 1 single wafer. You can multiply that by 25 cause of the number of wafers per cassette. (1260x25x$1000. per 45min)=The value of screwing up or missing a step.
3)The "Boat" are then sent to "Litho" with there fresh coat of resist and slam. The wafer under go a exposure process "Same as developing a negative from film" Once that is complete it's back over to etch.
4)Before the etching process can begin. The slam material needs to be removed. If this is not done, you just contaminated 250 million dollar etch process tool. 12hrs to recover from that kind of contamination refer back to the equation up above. The wafer need to go back to "Wetbench" as we call it and needs a EG3 bath. "Ethelyn Glycol Proprietary blend" This removes the slam material with out impacting the resist.
5) Wafers are then moved from the wetbench in etch onto metal etch tool named "Telius" made by "Tokyo Electron Ltd". Metal oxide etch process is done to create a trench. Each wafer is removed from the cassette by way of robotic actuation. Inside the process chamber there is a ceramic chuck the wafer will sit on during the etch process. First as the wafer is being delivered to the process chamber there are 3 lifter pins "Very Small" the arm will set the wafer down on. Once the arm is removed there is a chamber door that closes. Once the door is closed the atmosphere is pumped out and a vacuum created inside the chamber. The lifter pins gently set the wafer down on the chuck (Deviation is <1micron) Once the wafer properly seated on the chuck(Measured by backside vacuum pressure) 1500vdc is applied to back side of the wafer to apply static charge to hold the wafer in place during the etching process. Deionized water and helium circulate through the chuck to provide cooling provided by tools located in the sub-fab below. Plasma is introduced in the process chamber and is focused by set of 32 rotating magnets upper set and a lower set. There is a upper electrode that supplies process gas and voltage "shower head" and the lower electrode "chuck" is for holding the wafer in place. This focuses the plasma directly to the surface of the wafer and prevents over etch.
6)Etch process done, time to get ride of the resist left over and clean the resist residue in our newly formed trenches where copper is going to be applied later. Wetbench will dunk all 25 wafers in 3 types of solutions and then dried at the end of the process. The wafers are then sent to plannar
7)Plannar applies very thin layer of copper and at this point plannar is done for now.
8)wafer move over to(KLA) a doping bench. Very large machine bombards the wafers with negative or positive charged ions. Making this metal layer more positive or less positive charged. It represent what type of current we want from one metal layer to the next via ILD layer. (I.E if you want transistors to fire sooner or later.) Think LC/RC time Constance or PNP transistor where one metal layer is the emitter, the next metal layer is the base, and the next metal layer is collector.
Depending on the metal layer this create that (K)dielectic portion you might have been talking about. Still not sure what you meant by (K) interconnects?
9) Wafers are then sent back over to plannar to have the remaining copper removed and polished to point your left with perfect metal copper lines running the entire metal1 layer of a die. Each copper line representing .
10)Wafers are sent back over to ILD to have insulated layer spun on to the surface of the wafer. ILD protects the next layer of copper to be put on the surface wafer. The same time providing the interconnects.
11)Essential in extreme layman terms that is Metal1 step, Metal2 step. Wash, Rinse, and Repeat 7 more times.
-The theoretical limit for CMOS manufacturing is about 0.5 nm process technology, according to the ITRS, but you're free to correct me, the 2010 posts are - 2010 Update.
Theoretical for CMOS maybe and they use the word "manufacturing". Once again talking about limitation of production size of entire device "CMOS" transistor based infrastructure xyz. If you talk about architecture your in a completely different field and were back down to 7nm and 13nm.structures. Only limitation is the the Lithography.
-Samsung achieved 22 nm memory manufacturing just within the last year, and work is afoot to get to sub-20 nm processes earlier than the ITRS roadmap suggested.
LMAO, wippie freaking doo doo? 22nm for memory. Samsung should already be down to least 18nm or 13nm for memory silicon. When they have to pack as many transistors in a modern CPU and then back it up with 12mb L1 cache memory and operate at 2.9Ghz and have 6 of them in 22nm technology. Then we can talk memory silicon vs CPU silicon. Until then "apples and oranges" when comes to comparing memory to cpu manufacturing. The next proc already scheduled to be released after "Sandy" later this year will be 22nm technology.
-Qualcomm is a fabless company, if we look only at their semiconductor side. Did you also know that some of Qualcomm work is contracted out to TriQuint. I work in Hillsboro, OR. at place called (PTD) Portland Technology Development at Intel corporation (Fab D1D). Anyway, back to TriQuint there semiconductor fab is located right behind our fab. I think it might have to do with us being located in a silicon forest or something? Some of the conversation you can have with those TriQuint guys over launch is amazing. Get back on point here. Namely the Wifi radio and our beloved 4G radio for EVO 4G was manufactured at TriQuant(Who knew?). Wouldn't you know some of the silicon being contracted out for manufacturing for EVO 3D is being handled at TriQuint as well. Amazing! Whoo Knew!!!
Qualcomm and TSMC Collaborating on 28nm Process Technology
TSMC's Fab 6 Production Exceeds 70,000 8-inch Wafers per Month
Not only TSMC using ancient 8in (200mm) wafer technology, but 70,000 wafers doesn't even come close to what our fab (D1D) does. Intel works compressed work weeks 12hr shifts 3 on 4 and vice verse. 24x7 operation in other words. I saw 110k wafers processed in a single shift there will be questions being asked because that tells me Process Tool went down and held up the line. Safety/Quality red flag goes off and answers need to be quick. Remember the IBM story in the beginning of this jovial little trot down non EVO 3D lane? Intel D1D fab will process 250k per day. I hope what ever it is TSMC is making for Qualcomm it's not important, at that rate we wont see it until next Xmas in mass quanity.
-Evidently, you don't work in hardware or in hardware supply.
-Neither are you familiar with semiconductor manufacturing. Nothing is
Your comment on me not knowing hardware. I will handle it like the rest comment with "No Comment". EarlyMon, I will take your approach and use your words of wisdom "all comes out in the wash."
EarlyMon, only responded to your post out sheer boredom, with no ambitions of trying make a point. I felt your post provided the perfect example with out me needing to write a book about nothing to do with EVO 3D.
The tone, I hope came off light hearten as it was meant to be.
Lastly, I am feeling groovy. I stepped down full time work at Intel shortly after EVO 4G launch. (Still pop in for meetings) I and some of my partners started up a consulting firm. Our group was ask to come back under contract (Labor Law thing) by a company wanting to be remain nameless to provide developer feed back. Course a chance to play with latest technology is what we live for it around here. Everyone was happy to back on board with the project. Some of the gizmos and gadgets I posted about earlier are working there way into EVO 3D. Time to pack it in call it a early day.
Cheers,
(>-_0<)BSOD
