Root [Kernel][Test] Stable at 1.8 Ghz

[animania260]

Okay, after a week and half of being lazy after setting up my Fedora machine to test compiling a custom kernel for the Rush.

I just test compiled this one with just a couple entry's to the acpuclock-7x30.c file which may (or may not) allow for overclocking..

I'm am not a Developer and do not claim to be. I just finish building this kernel and wanted to others that have experiences and know how to check out what I added to the acpuclock-7x30.c

(Shabby and others)

I have no idea how these tables work.. Our Rush runs at 1024 mhz but the table (before I modified it even) goes up to 1400 MHZ but obviously in System Tuner and etc, you can't go over 1024 MHZ. I don't understand that since there is other freg' in there, though I guessed somewhere they just are not enabled for our phone or something. So hopefully Shabby and the other pro's can help me out here when they have time.

I'm not testing this untill I get info from people who know what they are doing here. As Shabby stated in the other thread on OC kernel he advised him what to do so. Those guys know and they are awesome and should be given the credit for a lot done on this forum..
I'm just compiling the kernel.. It's not hard.

I only added these two lines:

{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[5]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1350), &pll2_tbl[6]},

(whole table)

static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576, LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
{ 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
{ 0, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 900, VDD_RAW(900) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
/* AXI has MSMC1 implications. See above. */
{ 1, 768000, PLL_1, 2, 0, 153600000, 1050, VDD_RAW(1050) },
/*
* AXI has MSMC1 implications. See above.
*/
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[0]},
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[1]},
{ 1, 1200000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[2]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[3]},
{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[5]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1300, VDD_RAW(1350), &pll2_tbl[6]},
{ 0 }
};

So just waiting for some feedback on this.

Now that I'm not being lazy I'm going to add some patches to the kernel to enable more governors, schedulers, hopefully ZRam possibly and others.

Edit: Alright, talked to Shabby and he sent me a link to some kernel source for a different phone with the same chip set (OC Kernel) and will be testing this soon.

Update: Tested stable at 1.8 GHZ :smokingsomb:

 

[rbheromax]

As much as I shouldnt be talking about kernels through my epic fails, the src from Samsung actually compiles

 

[rbheromax]

Slayer72, quite frankly I believe I fried your CPU, because I seriously overvolted. If you look and see how His VDD RAW only goes to 1300, I went way higher. You should do like I did, go and read everything you can find on pll and voltage. After some time on that the table will make sense.

 

[rbheromax]

Wish I could bro, when I get my posting privileges back, ima dedicate my first few posts back, in your honor

 

[Lordvincent 90]

Retracted

 

[rbheromax]

I'm pretty sure he was just kidding, everyone around here should know the rules

 

[animania260]

Just confirmed a stock (but optimized with make -o2) build works building from source.
About to test an OC kernel

 

[rbheromax]

What sources r u using?

 

[animania260]

update 2 source (LK7) for our phone from the Samsung source site. I've had the build for day's but been having problems getting it to flash because of the updater-script.. not used to the syntax

 

[rbheromax]

Same source I was using, did u grab the modules that were built?, and grab a few roms from other devices and see how their update scripts work, any of the original galaxy s line have a vast library of roms

 

[animania260]

Okay I mergerd the source from this kernel (just added what they changed in 3 files for OC)
I am running at 1.8 Ghz right now (which I forgot to change the defaults for before I built the kernel) but it's actually stable.. and fast. However for some reason it's not letting me change the clock in System Tuner and say's "Failed to set CPU settings" perhaps a different CPU program should be used.

I'm going to set the default to 1.4 or maybe 1.2 and upload the kernel. Also with make -o2 it really helps with lower memory usage on boot-up from what I've seen so far so I'm going to build with
make -o3 and see how that runs (most optimized)

We got on OC kernel!!
Once I get it defaulted to 1.4 I'll upload. I still need to test and get a working flashable zip though.. which is being a PITA...

Now just need to get some more governors and schedulers and a few other things.

kernel source Shabby pointed me to, it has the chip the Rush has.
https://github.com/downthemachine/N861_ZTE_kernel/

 

[rbheromax]

Good job
Can u post your freq table here? I would really like to see how u did it

Sent from my HERO200 using Tapatalk 2

 

[animania260]

Yeah when I get back from lunch. It's the acpuclock7x30 in the link above though. Same one you edited

 

[rbheromax]

Thanks, Really all I needed was the the value you used for the top voltage level, I set mine to 1450 mV which I believe is the reason for bricking
Now I can see what I did wrong and learn from my mistakes

Sent from my HERO200 using Tapatalk 2

 

[animania260]

Yeah I don't think that's what did in Slayer's phone though because im running at 1450 mv right now. And it's completely stable and is not even getting hot.

This isin't all that was added to the file as the guy that I got the source from put in some code to set the default value at, but here is the table.

static struct pll pll2_tbl[] = {
{ 42, 0, 1, 0 }, /* 806 MHz */
{ 48, 1, 3, 0 }, /* 921 MHz */
{ 53, 1, 3, 0 }, /* 1024 MHz */
{ 58, 1, 3, 0 }, /* 1113 MHz */
{ 63, 1, 3, 0 }, /* 1209 MHz */
{ 68, 1, 3, 0 }, /* 1305 MHz */
{ 73, 1, 3, 0 }, /* 1401 MHz */
{ 78, 1, 3, 0 }, /* 1516 MHz */
{ 83, 1, 3, 0 }, /* 1612 MHz */
{ 88, 1, 3, 0 }, /* 1708 MHz */
{ 93, 1, 3, 0 }, /* 1804 MHz */
};

/* Use negative numbers for sources that can't be enabled/disabled */

enum acpuclk_source {
LPXO = -2,
AXI = -1,
PLL_0 = 0,
PLL_1,
PLL_2,
PLL_3,
MAX_SOURCE
};

static struct clk *acpuclk_sources[MAX_SOURCE];

/*
* Each ACPU frequency has a certain minimum MSMC1 voltage requirement
* that is implicitly met by voting for a specific minimum AXI frequency.
* Do NOT change the AXI frequency unless you are _absoulutely_ sure you
* know all the h/w requirements.
*/
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576, LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
{ 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
{ 0, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 900, VDD_RAW(900) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
{ 0, 460800, PLL_1, 2, 0, 153600000, 900, VDD_RAW(900) },
{ 0, 576000, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 0, 652800, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 768000, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
/*
* AXI has MSMC1 implications. See above.
*/
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000), &pll2_tbl[0]},
{ 1, 921600, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000), &pll2_tbl[1]},
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000), &pll2_tbl[2]},
{ 0, 1113000, PLL_2, 3, 0, UINT_MAX, 1050, VDD_RAW(1050), &pll2_tbl[3]},
{ 1, 1209600, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[4]},
{ 0, 1305600, PLL_2, 3, 0, UINT_MAX, 1150, VDD_RAW(1150), &pll2_tbl[5]},
{ 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[6]},
{ 1, 1516800, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[7]},
{ 1, 1612800, PLL_2, 3, 0, UINT_MAX, 1350, VDD_RAW(1350), &pll2_tbl[8]},
{ 1, 1708800, PLL_2, 3, 0, UINT_MAX, 1400, VDD_RAW(1400), &pll2_tbl[9]},
{ 1, 1804800, PLL_2, 3, 0, UINT_MAX, 1450, VDD_RAW(1450), &pll2_tbl[10]},
{ 0 }
};

 

[sckboy78]

Thanks bro for all your work on getting us this looking forward to it.

 

[animania260]

Np man. Glad I can finally contribute to something. I need help getting a damn flashable zip though.
I'm going to set the default that I forgot to set and I'll upload the boot.img.

Right now I'm just using the Super Stock ICS zip and replacing the boot.img in the zip to flash it. I'll mess with geting a flashable at least just for the boot.img tonight after work though.

 

[rbheromax]

For help on the flqshqble zip look at hroarks or koumajutsus kernels for the prevail, tweak the updater-script replace the boot.img

Sent from my HERO200 using Tapatalk 2

 

[animania260]

Thanks, I'm trying a slightly modified Kouma updater-script.
Going to test a new 1.8Ghz build and 1.4Ghz build with make -o3 optimizations and if all goes well I'll upload both. I wouldn't recommend 1.8ghz but it's running really well..

 

[rbheromax]

Cool, is battery life affected, and Are u going to change the boot splash?

Sent from my HERO200 using Tapatalk 2

 

[sckboy78]

Send me the boot.img if you don't mind. I wanna test it on Party ROM. Just shoot me a pm

 

[animania260]

For now it's just stock kernel with OC and optimized slightly with make -o3 which actually is most optimized (adds compiler optimizations). I'll be adding more later.

 

[rbheromax]

Is there any chance of a linaro optimized?

 

[animania260]

Yes I will be building with Linaro soon!

 

[rbheromax]

Just what I was craving, lol